The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method of patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices.
Transistor gate electrodes made of doped polysilicon have long been used in the manufacture of metal oxide semiconductor (MOS) transistors. The use of doped polysilicon gates becomes problematic, however, as the dimensions of gates and gate dielectrics are reduced. In particular, small polysilicon gates can accommodate only a finite amount of dopant material. This limitation can in turn result in a depletion of gate charge carriers at the interface between the gate and gate insulator (dielectric), when the gate electrode of a device is biased to invert the channel. Consequently, the electrical thickness of the gate dielectric is substantially increased, thereby deteriorating the performance characteristics of the transistor, such as reducing the drive current and switching speed. Depletion of the polysilicon gate is thus a fundamental issue that limits further scaling of MOS devices.
Metal gate stacks are an attractive alternative to polysilicon gates since they have a larger supply of charge carriers than doped polysilicon gates. One existing type of metal gate stack structure includes both a lower metal layer and an upper polysilicon layer. When a metal gate stack is inverted, there is no substantial depletion of carriers at the interface between the metal gate layer and the gate dielectric. Accordingly, the transistor's performance is not deteriorated because the electrical thickness of the gate stack is not increased.
On the other hand, the fabrication of such metal gate stack structures presents its own set of unique challenges, such as the problem of metal foot formation at the bottom of the stack, resulting from standard metal gate etch processing. More specifically, for so called “gate first” integration schemes, a thin metal layer (e.g., TiN) is deposited over a gate insulating layer and substrate, followed by a thicker layer of polysilicon. A gate stack structure is then patterned using either a hardmask or softmask approach. Using conventional etch techniques, chemistries such as HBr or Cl are introduced in order to etch both the polysilicon layer and metal layer of the gate stack. Unfortunately, the etch chemistry used in etching the polysilicon layer has poor etch selectivity with respect to the underlying metal layer in the stack. Thus, differences in the chemical reactivity of metal and polysilicon during the polysilicon overetch lead to a degraded gate stack profile (e.g., polysilicon footing, metal footing, metal undercutting, etc.)
As is known in the art, the gate stack structure determines (in part) the source/drain extension implant and diffusion profile. Ideally, the extension profile is highly abrupt, and is achieved only when the gate profile is straight. In the case of metal foot formation, problems in addition to non-ideal source/drain extension and diffusion profiles also arise. For example, with conventional metal gate reactive ion etch (RIE) methods, the footing is not uniform or consistent within a single wafer, or from wafer to wafer for that matter. Such variations lead to uncontrollable extension profiles that in turn cause voltage threshold (Vt) variations that are unacceptable from a performance and manufacturing standpoint. In addition, metal footing also adds to outer fringe capacitance, which also degrades circuit performance. Simulations have shown that the presence of a metal foot in a transistor gate can add about 0.03-0.04 fF/μm per side, which in turn results in up to about 8% loss in circuit performance.
Accordingly, it would be desirable to be able to implement an improved method of metal gate stack patterning in a manner that addresses the problems created by degraded stack profiles, including those attributed to metal foot formation following the etching of the metal layer in the gate stack.